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fedd51v17400j-01 issue date: mar. 31, 2011 msm51v17400j 4,194,304-word ? 4-bit dynamic ram : fast page mode type 1/15 description the msm51v17400j is a 4,194,304-word ? 4-bit dynamic ram fabricated in oki semiconductor?s silicon-gate cmos technology. the msm51v17400j achieves high integration, high-speed operation, and low-power consumption because oki semiconductor manufactures the device in a quadruple-layer polysilicon/double- layer metal cmos process. the msm51v17400j is available in a 26/24-pin plastic soj, 26/24-pin plastic tsop. features 4,194,304-word ? 4-bit configuration single 3.3v power supply, ? 0.3v tolerance input : lvttl compatible, low input capacitance output : lvttl compatible, 3-state refresh : 2048 cycles/32ms fast page mode, read modify write capability cas before ras refresh, hidden refresh, ras -only refresh capability packages 26/24-pin 300mil plastic soj ( soj26/24-300-1.27 ) (product : msm51v17400j-xxsj) 26/24-pin 300mil plastic tsop ( tsopii26/24-300-1.27-3k ) (product : msm51v17400j-xxts-k) xx indicates speed rank.. product family access time (max.) power dissipation family t rac t aa t cac t oea cycle time (min.) operating (max.) standby (max.) msm51v17400j-50 50 ns 25 ns 13 ns 13 ns 90 ns 360mw msm51v17400j-60 60 ns 30 ns 15 ns 15 ns 110 ns 324mw msm51v17400j-70 70 ns 35 ns 20 ns 20 ns 130 ns 288mw 1.8mw
fedd51v17400j-01 msm51v17400j 2/15 pin configuration (top view) pin name function a0?a10 address input ras row address strobe cas column address strobe dq1?dq4 data input/data output oe output enable we write enable v cc power supply (3.3v) v ss ground (0v) nc no connection note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 dq1 dq2 v cc v cc v ss v ss dq4 dq3 a 9 a 8 a 7 a 6 a0 a1 a2 a3 we ras nc a10 a 5 a 4 cas oe 26/24-pin plastic tsop (k type) 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 dq1 dq2 v cc v cc v ss v ss a 9 a 8 a 7 a 6 a0 a1 a2 a3 we ras nc a10 a 5 a 4 oe dq4 dq3 cas 26/24-pin plastic soj
fedd51v17400j-01 msm51v17400j 3/15 electrical characteristics absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out ?0.5 to v cc + 0.5 v voltage v cc supply relative to v ss v cc ?0.5 to 4.6 v short circuit output current i os 50 ma power dissipation p d* 1 w operating temperature t opr 0 to 70 c storage temperature t stg ?55 to 150 c *: ta = 25 ? c recommended operating conditions (ta = 0 to 70c) parameter symbol min. typ. max. unit v cc 3.0 3.3 3.6 v power supply voltage v ss 0 0 0 v input high voltage v ih 2.0 ? v cc + 0.3 *1 v input low voltage v il ? 0.3 *2 ? 0.8 v notes: *1. the input voltage is v cc + 1.0v when the pulse width is less than 20ns (the pulse width is with respect to the point at which v cc is applied). *2. the input voltage is v ss ? 1.0v when the pulse width is less than 20ns (the pulse width respect to the point at which v ss is applied). pin capacitance (vcc = 3.3v ? 0.3v, ta = 25c, f = 1 mhz) parameter symbol min. min. unit input capacitance (a0 ? a10) c in1 ? 5 pf input capacitance ( ras , cas , we , oe ) c in2 ? 7 pf output capacitance (dq1 ? dq4) c i/o ? 7 pf
fedd51v17400j-01 msm51v17400j 4/15 dc characteristics (v cc = 3.3v ? 0.3v, ta = 0 to 70c) msm51v17400 j-50 msm51v17400 j-60 msm51v17400 j-70 parameter symbol condition min. max. min. max min. max. unit note output high voltage v oh i oh = ? 2.0ma 2.4 v cc 2.4 v cc 2.4 v cc v output low voltage v ol i ol = 2.0ma 0 0.4 0 0.4 0 0.4 v input leakage current i li 0v ? v i ? v cc +0.3v; all other pins not under test = 0v ? 10 10 ? 10 10 ? 10 10 ? a output leakage current i lo dq disable 0v ? v o ? v cc ? 10 10 ? 10 10 ? 10 10 ? a average power supply current (operating) i cc1 ras , cas cycling, t rc = min. ? 100 ? 90 ? 80 ma 1,2 ras , cas = v ih ? 2 ? 2 ? 2 power supply current (standby) i cc2 ras , cas ? v cc ? 0.2v ? 0.5 ? 0.5 ? 0.5 ma 1 average power supply current ( ras -only refresh) i cc3 ras cycling, cas = v ih , t rc = min. ? 100 ? 90 ? 80 ma 1,2 power supply current (standby) i cc5 ras = v ih , cas = v il , dq = enable ? 5 ? 5 ? 5 ma 1 average power supply current ( cas before ras refresh) i cc6 ras = cycling, cas before ras ? 100 ? 90 ? 80 ma 1,2 average power supply current (fast page mode) i cc7 ras = v il , cas cycling, t pc = min. ? 75 ? 70 ? 65 ma 1,3 notes: 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih .
fedd51v17400j-01 msm51v17400j 5/15 ac characteristics (1/2) (v cc = 3.3v ? 0.3v, ta = 0 to 70c) note1,2,3,11,12 msm51v17400 j-50 msm51v17400 j-60 msm51v17400 j-70 parameter symbol min. max. min. max. min. max. unit note random read or write cycle time t rc 90 ? 110 ? 130 ? ns read modify write cycle time t rwc 131 ? 155 ? 185 ? ns fast page mode cycle time t pc 35 ? 40 ? 45 ? ns fast page mode read modify write cycle time t prwc 76 ? 85 ? 100 ? ns access time from ras t rac ? 50 ? 60 ? 70 ns 4, 5, 6 access time from cas t cac ? 13 ? 15 ? 20 ns 4, 5 access time from column address t aa ? 25 ? 30 ? 35 ns 4, 6 access time from cas precharge t cpa ? 30 ? 35 ? 40 ns 4 access time from oe t oea ? 13 ? 15 ? 20 ns 4 output low impedance time from cas t clz 0 ? 0 ? 0 ? ns 4 cas to data output buffer turn- off delay time t off 0 13 0 15 0 20 ns 7 oe to data output buffer turn-off delay time t oez 0 13 0 15 0 20 ns 7 transition time t t 3 50 3 50 3 50 ns 3 refresh period t ref ? 32 ? 32 ? 32 ms ras precharge time t rp 30 ? 40 ? 50 ? ns ras pulse width t ras 50 10,000 60 10,000 70 10,000 ns ras pulse width (fast page mode) t rasp 50 100,000 60 100,000 70 100,000 ns ras hold time t rsh 13 ? 15 ? 20 ? ns ras hold time referenced to oe t roh 13 ? 15 ? 20 ? ns cas precharge time (fast page mode) t cp 7 ? 10 ? 10 ? ns cas pulse width t cas 13 10,000 15 10,000 20 10,000 ns cas hold time t csh 50 ? 60 ? 70 ? ns cas to ras precharge time t crp 5 ? 5 ? 5 ? ns ras hold time from cas precharge t rhcp 30 ? 35 ? 40 ? ns ras to cas delay time t rcd 17 37 20 45 20 50 ns 5 ras to column address delay time t rad 12 25 15 30 15 35 ns 6 row address set-up time t asr 0 ? 0 ? 0 ? ns
fedd51v17400j-01 msm51v17400j 6/15 ac characteristics (2/2) (v cc = 3.3v ? 0.3v ,ta = 0 to 70c) note1,2,3,11,12 msm51v17400 j-50 msm51v17400 j-60 msm51v17400 j-70 parameter symbol min. max. min. max. min. max. unit note row address hold time t rah 7 ? 10 ? 10 ? ns column address set-up time t asc 0 ? 0 ? 0 ? ns column address hold time t cah 7 ? 10 ? 15 ? ns column address to ras lead time t ral 25 ? 30 ? 35 ? ns read command set-up time t rcs 0 ? 0 ? 0 ? ns read command hold time t rch 0 ? 0 ? 0 ? ns 8 read command hold time referenced to ras t rrh 0 ? 0 ? 0 ? ns 8 write command set-up time t wcs 0 ? 0 ? 0 ? ns 9 write command hold time t wch 7 ? 10 ? 15 ? ns write command pulse width t wp 7 ? 10 ? 10 ? ns oe command hold time t oeh 13 ? 15 ? 20 ? ns write command to ras lead time t rwl 13 ? 15 ? 20 ? ns write command to cas lead time t cwl 13 ? 15 ? 20 ? ns data-in set-up time t ds 0 ? 0 ? 0 ? ns 10 data-in hold time t dh 7 ? 10 ? 15 ? ns 10 oe to data-in delay time t oed 13 ? 15 ? 20 ? ns cas to we delay time t cwd 36 ? 40 ? 50 ? ns 9 column address to we delay time t awd 48 ? 55 ? 65 ? ns 9 ras to we delay time t rwd 73 ? 85 ? 100 ? ns 9 cas precharge we delay time t cpwd 53 ? 60 ? 70 ? ns 9 cas active delay time from ras precharge t rpc 5 ? 5 ? 5 ? ns ras to cas set-up time ( cas before ras ) t csr 10 ? 10 ? 10 ? ns ras to cas hold time ( cas before ras ) t chr 10 ? 10 ? 10 ? ns we to ras precharge time ( cas before ras ) t wrp 10 ? 10 ? 10 ? ns we hold time from ras ( cas before ras ) t wrh 10 ? 10 ? 10 ? ns
fedd51v17400j-01 msm51v17400j 7/15 notes: 1. a start-up delay of 200 ? s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5ns. 3. v ih (min.) and v il (max.) are reference levels for measur ing input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 1ttl load and 100pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) and t oez (max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating paramete rs. they are included in the data sheet as electrical characteristics only. if t wcs ? t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd ? t cwd (min.), t rwd ? t rwd (min.), t awd ? t awd (min.) and t cpwd ? t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then th e condition of the data out (at access time) is indeterminate. 10. these parameters are referenced to the cas , leading edges in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 11. the test mode is initiated by performing a we and cas before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is ge nerated. in a test ca9 and ca10 are not used and each dq pin now access 4-bit lo cations. since all 4 dq pins are used, a total 16 data bits can be written in parallel into the memory array. in a read cycle, if 4 data bits are equal, the dq pin will indicate a high level. if the 4 data bits are not equal, the dq pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operating state by performing a ras -only refresh cycle or a cas before ras refresh cycle. 12. in a test mode read cycle, the value of access time parameter is delayed for 5n s for the specified value. these parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
fedd51v17400j-01 msm51v17400j 8/15 timing chart read cycle write cycle (early write) t off t clz t cac t oea t asc t rrh t rah t asr t rad t ral t crp t cah t crp t rcd t rc t ras t rp t csh t rsh t cas t rac t aa t rcs t roh t rch t oez ro w column valid data-out o p en ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol ?h? or ?l? t crp t rp t rwl valid data-in t d t ds t wcs t wch t cwl t asr t rah t asc t rc t ras ro w t csh t crp t rcd t rsh t cas column t cah t rad t ral t wp ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v ih v il ?h? or ?l? open
fedd51v17400j-01 msm51v17400j 9/15 read modify write cycle t rsh t cas t rwc t cwl t rwl t crp t rp t oed t cwd t awd t oeh t wp t oez t cac t dh t ds valid data-out valid d a t a -in t aa t rwd ro w colum t rac t oe t rcs t cah t asc t asr t rah t rad t crp t rcd t csh t ras t clz ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v i/oh v i/ol ?h? or ?l?
fedd51v17400j-01 msm51v17400j 10/15 fast page mode read cycle fast page mode write cycle (early write) t wp t cwl t wch t asc t cp t pc t rasp column t ral t crp t asc t cah t cah t cas t rsh t cp t cas t rp t rhpc column t wp t wch t dh t ds t dh t ds valid * data-in t wcs t wcs valid * data-in t cwl t csh t rad t asr t asc t rah t rcd t crp t cas t cah ro w column t wp t rwl t wch t cwl t dh t ds t wcs valid * data-in ?h? or ?l? ra s v ih v il ca s v ih v il address v ih v il w e v ih v il dq v ih v il note: oe = ?h? or ?l? t pc t cas t oez t cac t off t cac t clz t oea t csh t cac t oez t rrh t rac t oea t ral t asc t cah t rcs t rch t cpa t aa t aa t rch t rcs t cah t asc t rah t rad t rcs t asr t asc t cp t cas t rsh t rasp t cas t cp t rcd t crp t clz t cah valid data-out t cpa t rp ras v ih v il cas v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol t rhcp ro w column column column ?h? or ?l? t crp t rch t aa t oea t off t oez valid data-out t clz t off valid data-out
fedd51v17400j-01 msm51v17400j 11/15 fast page mode read modify write cycle ras -only refresh cycle t ds t aa t dh t roh t oea t wp t cpa t ds t oez t cpwd t wp t cwd t awd t dh t awd t aa t rac t rcs t rcs t aa t cpa t oea t rwd t cwd t asc t rah t asr t rad t csh t cas t rasp t cwl t rcd t cp t cah t asc row column t rwl t cwl t rc column t cwl t cwd t ral t cah t cr t cp t cas t clz t cas t asc t oed t oez t oed t cac t oed t dh t oez in t wp t ds column t rp t rsh t cah out t cac t prwc t cac t clz t clz t awd t oea in in out out t cpwd ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v i/oh v i/ol ?h? or ?l? note: in = valid data-in, out = valid data-out t asr t ra t crp t rpc t rp t ras t rc t off ro w ras v ih v il ca s v ih v il v ih v il address v oh v ol dq ?h? or ?l? o p en note: we , oe = ?h? or ?l?
fedd51v17400j-01 msm51v17400j 12/15 cas before ras refresh cycle hidden refresh read cycle t wrh t wrp t wrp t off t rpc t rp t rc t ras t chr t csr t rp t cp t rpc ras v ih v il cas v ih v il v oh v ol dq o p en note: oe , address = ?h? or ?l? w e v ih v il ?h? or ?l? t rac t clz t oez t roh t oea t cac t rrh t aa t ral t rcs t cah t rah t asr t asc column t rad t rp t ras t rc t rp t chr t ras t rsh t rcd t crp t rc ras v ih v il cas v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol o p en ro w valid data-out ?h? or ?l? t off t wrp t wrh
fedd51v17400j-01 msm51v17400j 13/15 hidden refresh write cycle test mode-in cycle t off t wts t wth t cp t rpc t csr t rp t chr t ras t rc ras v ih v il cas v ih v il w e v ih v il dq v ih v il ?h? or ?l? open note: oe , address = ?h? or ?l? t dh t ds t wch t wcs t rwl t ral t rad t cah t rah t asr t asc t rcd t crp t rsh t rp t chr t rp t ras t rc t rc t ras t wp ras v ih v il cas v ih v il address v ih v il w e v ih v il o e v ih v il dq v ih v il ro w column valid data-in ?h? or ?l? t wrp t wrh
fedd51v17400j-01 msm51v17400j 14/15 revision history page document no. date previous edition current edition description fedd51v17400j-01 mar.31, 2011 ? ? 1st edition
fedd51v17400j-01 msm51v17400j 15/15 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the ac tual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to , operating voltage, power dissipation, and operating temperature. 4. oki semiconductor assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handli ng, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s in dustrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability char acteristics nor in any system or ap plication where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, tr affic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2011 oki semiconductor co., ltd.

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